UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 177
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 177 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
5.3
memory space. The programmable wait function and bus cycle operation mode for each of these blocks can be
independently controlled in one-block units.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
The 16 MB external memory space is divided into memory blocks of 2 MB, 4 MB, and 8 MB from the lowest of the
Notes 1. CS1 is not provided as an external signal of the V850ES/Jx3-U; it is used internally as a chip select
Memory Block Function
0 3 F F F F F F H
0 3 F E C 0 0 0 H
0 3 F E B F F F H
0 1 0 0 0 0 0 0 H
0 0 F F F F F F H
0 0 8 0 0 0 0 0 H
0 0 7 F F F F F H
0 0 4 0 0 0 0 0 H
0 0 3 F F F F F H
0 0 2 0 0 0 0 0 H
0 0 1 F F F F F H
0 0 0 0 0 0 0 0 H
2. Use of addresses 03FEF000H to 03FEFFFFH is prohibited because these addresses are in the
3. This area is an external memory area in the case of a data write access.
signal for the USB.
same area as the on-chip peripheral I/O area.
External memory area
External memory area
External memory area
Use prohibited
(80 KB)
(8 MB)
(4 MB)
(2 MB)
(2 MB)
Figure 5-1. Data Memory Map: Physical Address
CS3
CS2
CS0
(CS1
Note 1
)
CHAPTER 5 BUS CONTROL FUNCTION
(Data-only RAM area)
Internal ROM area
External memory area
Use prohibited
USB function area
On-chip peripheral
Internal RAM area
USB host area
Use prohibited
Use prohibited
Use prohibited
I/O area (4 KB)
(60 KB)
(1 MB)
(1 MB)
Note 2
Note 3
0 3 F F F F F F H
0 3 F F F 0 0 0 H
0 3 F F E F F F H
0 3 F F 0 0 0 0 H
0 3 F E F F F F H
0 3 F E F 0 0 0 H
0 3 F E E F F F H
0 3 F E C 0 0 0 H
0 0 3 F F F F F H
0 0 3 0 0 0 0 0 H
0 0 2 F F F F F H
0 0 2 8 0 0 0 0 H
0 0 2 7 F F F F H
0 0 2 5 0 0 0 0 H
0 0 2 4 F F F F H
0 0 2 0 0 0 0 0 H
0 0 1 F F F F F H
0 0 1 0 0 0 0 0 H
0 0 0 F F F F F H
0 0 0 0 0 0 0 0 H
Page 177 of 1408
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