UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1203
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
23.5 Exception Trap
V850ES/JG3-U and V850ES/JH3-U, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an
exception trap.
23.5.1 Illegal opcode
23) = 0111B to 1111B, and sub-opcode (bit 16) = 0B. When such an instruction is executed, an exception trap is
generated.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
An illegal opcode is defined as an instruction with instruction opcode (bits 10 to 5) = 111111B, sub-opcode (bits 26 to
Caution It is recommended not to use an illegal opcode because instructions may newly be assigned in the
(1) Operation
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1.
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control.
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine.
The processing of the exception trap is shown below.
future.
×: Arbitrary
15
×
×
×
×
11
×
10
1
1
1
1
CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
1
5
1
×
4
×
×
×
×
0
31
×
×
×
×
27 26
×
0
1
1
1
to
1
1
23 22
1
1
× × × × × × 0
16
Page 1203 of 1408
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