UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 272
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 272 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(2) Operation timing in one-shot pulse output mode
External trigger input
INTTAAnCC0 signal
INTTAAnCC1 signal
(only when software
TAAnCCR0 register
TAAnCCR1 register
TOAAn0 pin output
TOAAn1 pin output
(a) Note on rewriting TAAnCCRm register
(TIAAn0 pin input)
trigger is used)
To change the set value of the TAAnCCRm register to a smaller value, stop counting once, and then change
the set value.
If the value of the TAAnCCRm register is rewritten to a smaller value during counting, the 16-bit counter may
overflow.
16-bit counter
When the TAAnCCR0 register is rewritten from D
D
greater than D
than D
compared with the count value. The counter counts up to FFFFH and then counts up again from 0000H.
When the count value matches D
pin. When the count value matches D
TOAAn1 pin, and stops counting.
Therefore, the counter may output a pulse with a delay period or active period different from that of the one-
shot pulse that is originally expected.
Remark
00
TAAnCE bit
> D
FFFFH
0000H
01
01
and less than D
and D
n = 0 to 3, 5
m = 0, 1
11
10
and less than D
> D
11
, if the TAAnCCR1 register is rewritten when the count value of the 16-bit counter is
00
Delay
(D
, each set value is reflected as soon as the register has been rewritten and
D
10
10
)
Active level width
(D
10
11
00
and if the TAAnCCR0 register is rewritten when the count value is greater
, the counter generates the INTTAAnCC1 signal and asserts the TOAAn1
D
− D
00
10
+ 1)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
01
D
, the counter generates the INTTAAnCC0 signal, deasserts the
10
D
00
Delay
(D
00
D
10
10
)
Active level width
(D
to D
00
D
− D
01
00
10
and the TAAnCCR1 register from D
+ 1)
D
Delay
(10000H + D
10
D
00
11
)
Active level width
(D
D
D
D
11
11
01
01
D
− D
01
11
Page 272 of 1408
+ 1)
10
to D
11
where
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