UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 220

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(5) TAAn I/O control register 2 (TAAnIOC2)
The TAAnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal
(TIAAn0 pin) and external trigger input signal (TIAAn0 pin).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
(n = 0 to 3, 5)
TAAnIOC2
After reset: 00H
Cautions 1. Rewrite the TAAnEES1, TAAnEES0, TAAnETS1, and
TAAnEES1
TAAnETS1
0
0
1
1
0
0
1
1
7
0
TAAnEES0
TAAnETS0
2. The TAAnEES1 and TAAnEES0 bits are valid only when
3. The TAAnETS1 and TAAnETS0 bits are valid only when
R/W
TAAnETS0 bits when the TAAnCTL0.TAAnCE bit = 0. (The
same value can be written when the TAAnCE bit = 1.) If
rewriting was mistakenly performed, clear the TAAnCE bit
to 0 and then set the bits again.
the TAAnCTL1.TAAnEEE bit = 1 or when the external
event
TAAnCTL1.TAAnMD0 bits = 001) has been set.
the
(TAAnCTL1.TAAnMD2 to TAAnCTL1.TAAnMD0 bits = 010)
or the one-shot pulse output mode (TAAnCTL1.TAAnMD2
to TAAnCTL1.TAAnMD0 = 011) is set.
6
0
0
1
0
1
0
1
0
1
Address:
External event count input signal (TIAAn0 pin) valid edge setting
No edge detection (external event count invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
No edge detection (external trigger invalid)
Detection of rising edge
Detection of falling edge
Detection of both edges
external
External trigger input signal (TIAAn0 pin) valid edge setting
count
5
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
TAA0IOC2 FFFFF634H, TAA1IOC2 FFFFF644H,
TAA2IOC2 FFFFF654H, TAA3IOC2 FFFFF664H.
TAA5IOC2 FFFFF684H
4
0
mode
trigger
TAAnEES1 TAAnEES0 TAAnETS1 TAAnETS0
3
(TAAnCTL1.TAAnMD2
pulse
2
output
1
mode
0
to
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