UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 319
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 319 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
7.7.1
TAA0 is used as the slave timer.
master timer is set to 1. The slave timer operates by the count clock supplied from the master timer (TAA1). After the
slave timer starts operating, however, the 16-bit counter of the slave timer (TAA0) is not cleared even if the 16-bit counter
of the master timer (TAA1) is cleared to 0000H upon a match between the 16-bit counter value of the master timer (TAA1)
and the TAA1CCR0 register value, because each timer operates individually.
register of the slave timer is not affected.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
In this section, the operation of the simultaneous-start function is shown, where TAA1 is used as the master timer and
The master timer (TAA1) and slave timer (TAA0) start operating at the same time when the TAA1CTL0.TAA0CE bit of
In the same manner, if the compare register value of the master timer (TAA1) is rewritten by batch writing, the compare
[Initial settings]
[Starting counting]
[End condition]
PWM output mode (simultaneous-start operation)
Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled)
Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled)
[Initial settings of master timer (TAA1)]
[Initial settings of slave timer (TAA0)]
Remark
<1> Set TAA1CTL0.TAA1CE of the master timer to 1.
<2> Start counting.
<3> Changing the setting of the register during operation
• Set TAA1CTL0.TAA0CE of the master timer to 0.
• TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 100 (setting of PMW output mode)
• TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any))
• TAA1CCR1, TAA1CCR0 (specification of valid edge of capture trigger)
• TAA1IOC0 (specification of valid edge of capture trigger)
• TAA0CTL1.TAA0SYE = 1, TAA0SYM = 1 (simultaneous-start operation)
• TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 100 (setting of PMW output mode)
• TAA0CCR0, TAA1CCR1 (specification of valid edge of capture trigger)
• TAA0IOC0 (specification of valid edge of capture trigger)
• The compare register can be rewritten (anytime write).
The initial settings of the master timer and slave timer may be performed in any order.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Page 319 of 1408
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