UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 870
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
19.12 Arbitration
IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is
adjusted until the data differs. This kind of operation is called arbitration (n = 0 to 2).
which the arbitration loss occurred, and the SCL0n and SDA0n lines are both set to high impedance, which releases the
bus (n = 0 to 2).
when a stop condition is detected, etc.) and the setting of the ALDn bit to 1, which is made by software (n = 0 to 2).
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Transfer lines
When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before the
When one of the master devices loses in arbitration, an arbitration loss flag (IICSn.ALDn bit) is set to 1 via the timing at
Arbitration loss is detected based on the timing of the next interrupt request signal (INTIICn) (the eighth or ninth clock,
For details of interrupt request timing, see 19.7 I
Master 1
Master 2
Remark
SDA0n
SDA0n
SDA0n
SCL0n
SCL0n
SCL0n
n = 0 to 2
Figure 19-14. Arbitration Timing Example
2
C Interrupt Request Signals (INTIICn).
Master 1 loses arbitration
CHAPTER 19 I
Hi-Z
Hi-Z
Page 870 of 1408
2
C BUS
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