UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 773

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(2) CSIFn control register 1 (CFnCTL1)
CFnCTL1 is an 8-bit register that controls the CSIFn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Caution The CFnCTL1 register can be rewritten only when the CFnCTL0.CFnPWR bit = 0.
(n = 0 to 4)
CFnCTL1
After reset: 00H
Notes 1. Set the communication clock (f
Remark
CFnCKS2
Communication
Communication
Communication
Communication
type 1
type 2
type 3
type 4
0
0
0
0
1
1
1
1
0
2. Set the communication clock (f
R/W
CFnCKS1
8 MHz or lower (master/slave mode).
When n = 0, 1, m = 1
When n = 2, 3, m = 2
When n = 4, m = 3
For details of f
CFnCKP
0
0
0
1
1
0
0
1
1
0
0
1
1
Address: CF0CTL1 FFFFFD01H, CF1CTL1 FFFFFD11H,
CFnCKS0
CFnDAP
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
0
1
0
1
0
1
0
1
0
1
0
1
0
BRGm
CF2CTL1 FFFFFD21H, CF3CTL1 FFFFFD31H,
CF4CTL1 FFFFFD41H
SOFn
SOFn (output)
SOFn
SOFn (output)
SIFn capture
SIFn capture
SIFn capture
SIFn capture
n = 0 to 2, 4
SCKFn
SCKFn
SCKFn
SCKFn
, see 18.8 Baud Rate Generator.
CFnCKP CFnDAP CFnCKS2 CFnCKS1 CFnCKS0
f
f
f
f
f
f
f
External clock (SCKFn)
XX
XX
XX
XX
XX
XX
BRGm
Communication clock (f
(output)
(output)
/3
/4
/6
/8
/32
/64
(I/O)
(I/O)
(I/O)
(I/O)
reception timing in relation to SCKFn
Specification of data transmission/
Note 1
D7
CCLK
D7
CCLK
D7
D7
f
f
f
f
f
f
) to 8 MHz or lower (master/slave mode).
XX
XX
XX
XX
XX
XX
D6
D6
) to 12 MHz or lower (master mode),
n = 3
/2
/4
/8
/16
/32
/64
D6
D6
D5
D5
Note 2
D5
D5
CCLK
D4
D4
)
D4
D4
D3
D3
D3
D3
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Master mode
Slave mode
D2
D2
D2
D2
Mode
D1
D1
D1
D1
D0
D0
D0
D0
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