UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 872
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
19.14 Communication Reservation
19.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0)
enable transmission of a start condition when the bus is released. There are two modes in which the bus is not used.
status is set after the bus is released (after the stop condition is detected).
address transfer to start. At this point, the IICCn.SPIEn bit should be set to 1 (n = 0 to 2).
according to the bus status (n = 0 to 2).
IICSn.MSTSn bit (n = 0 to 2).
SMCn, CLn1, and CLn0 bits of the IICCLn register and the IICXn.CLXn bit (n = 0 to 2).
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
To start master device communications when not currently using the bus, a communication reservation can be made to
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released
If the IICCn.STTn bit is set to 1 while the bus is not being used, a start condition is automatically generated and a wait
When the bus release is detected (when the stop condition is detected), writing to the IICn register causes master
When STTn has been set to 1, the operation mode (as start condition or as communication reservation) is determined
If the bus has been released .............................................A start condition is generated
If the bus has not been released (standby mode)..............Communication reservation
To detect which operation mode has been determined, set the STTn bit to 1, wait for the wait period, then check the
The wait periods, which should be set via software, are listed in Table 19-6. These wait periods can be set by the
when the IICCn.LRELn bit was set to 1) (n = 0 to 2).
CHAPTER 19 I
Page 872 of 1408
2
C BUS
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