UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 28

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
1.6
1.6.1
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
• V850ES/JG3-U
TOAA00 to TOAA30, TOAA50,
TOAA01 to TOAA31, TOAA51
Notes 1.
Function Block Configuration
TECR0, TENC00, TENC01,
TIAA00 to TIAA30, TIAA50,
TIAA01 to TIAA31, TIAA51,
Internal block diagram
TOAB1T1 to TOAB1T3,
TOAB1B1 to TOAB1B3
TOAB00 to TOAB03,
EVTT0, TIT00, TIT01
TOAB10 to TOAB13
2.
RXDC0 to RXDC4
TIAB00 to TIAB03,
TIAB10 to TIAB13,
TXDC0 to TXDC4
INTP07 to INTP18
SCKF0 to SCKF4
SDA00 to SDA02
RTP00 to RTP05
SCL00 to SCL02
INTP02, INTP05 ,
SOF0 to SOF4
μ
μ
μ
μ
TOT00, TOT01
PD70F3763:
PD70F3764:
PD70F3763:
PD70F3764:
SIF0 to SIF4
TOAB1OFF
TOAA1OFF
ASCKC0
TRGAB1,
RTC1HZ
EVTAB1,
RTCDIV
RTCCL
UDMH
UDMF
UDPH
PPON
UDPF
OCI
NMI
384 KB
512 KB
48 KB (Including a data only RAM: 8 KB)
56 KB (Including a data only RAM: 8 KB)
16-bit interval
USB function
16-bit timer/
counter AB:
16-bit timer/
counter AA:
16-bit timer/
counter T:
I
2
USB host
timer M:
UARTC
C0: 3 ch
INTC
WDT
CSIF
RTO
2 ch
6 ch
5 ch
5 ch
4 ch
1 ch
RTC
:
:
Flash memory
DMAC
Note 1
Note 2
RAM
Key return
converter
converter
function
D/A
A/D
Ports
registers 32 bits × 32
32-bit barrel
General-purpose
System
register
shifter
PC
KR0 to KR7
ANI0 to ANI11
ADTRG
AV
AV
AV
ANO0, ANO1
REF0
SS
REF1
CPU
Multiplier
16 × 16 → 32
ALU
CHAPTER 1 INTRODUCTION
DCU
Regulator
Instruction
queue
BCU
PLL
CG
CG
LVI
CLKOUT
XT1
XT2
X1
X2
RESET
V
V
REGC
FLMD0
FLMD1
EV
Page 28 of 1408
WR0, WR1
CS0, CS2, CS3
AD0 to AD15
ASTB
RD
WAIT
DD
SS
DRST
DMS
DDI
DCK
DDO
DD
, UV
DD