UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 284
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
and TOAAn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TAAnCCRm
register, a compare match interrupt request signal (INTTAAnCCm) is generated, and the output signal of the TOAAnm pin
is inverted.
generates an overflow interrupt request signal (INTTAAnOV) at the next clock, is cleared to 0000H, and continues
counting. At this time, the overflow flag (TAAnOPT0.TAAnOVF bit) is also set to 1. Clear the overflow flag to 0 by
executing the CLR instruction by software.
that time, and compared with the count value.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
When the TAAnCE bit is set to 1, 16-bit timer/event counter AA starts counting, and the output signals of the TOAAn0
The 16-bit counter continues counting in synchronization with the count clock. When it counts up to FFFFH, it
The TAAnCCRm register can be rewritten while the counter is operating. If it is rewritten, the new value is reflected at
INTTAAnCC0 signal
INTTAAnCC1 signal
TAAnCCR1 register
TAAnCCR0 register
Remark
TOAAn0 pin output
TOAAn1 pin output
INTTAAnOV signal
16-bit counter
TAAnOVF bit
TAAnCE bit
Figure 7-34. Basic Timing in Free-Running Timer Mode (Compare Function)
n = 0 to 3, 5
m = 0, 1
FFFFH
0000H
D
10
D
00
D
Cleared to 0 by
CLR instruction
10
D
00
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
D
10
D
00
CLR instruction
Cleared to 0 by
D
11
D
01
CLR instruction
Cleared to 0 by
D
11
D
D
D
01
01
11
CLR instruction
Cleared to 0 by
D
11
Page 284 of 1408
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