UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1222
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 1222 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(2) Power save mode register (PSMR)
Cautions 1. Be sure to set bits 2 to 7 to “0”.
Remark IDLE1:
The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock
operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
2. The PSM0 and PSM1 bits are valid only when the PSC.STP bit is 1.
IDLE2:
STOP:
Sub-IDLE: In this mode, all other operations are halted except for the oscillator. After the IDLE mode
PSMR
After reset: 00H
In this mode, all operations except the oscillator operation and some other circuits (flash
memory and PLL) are stopped.
After the IDLE1 mode is released, the normal operation mode is restored without needing
to secure the oscillation stabilization time, like the HALT mode.
In this mode, all operations except the oscillator operation are stopped.
After the IDLE2 mode is released, the normal operation mode is restored following the
lapse of the setup time specified by the OSTS register (flash memory and PLL).
In this mode, all operations except the subclock oscillator operation are stopped.
After the STOP mode is released, the normal operation mode is restored following the
lapse of the oscillation stabilization time specified by the OSTS register.
has been released by the interrupt request signal, the subclock operation mode will be
restored after 12 cycles of the subclock have been secured.
PSM1
0
0
1
1
0
PSM0
R/W
0
1
0
1
0
IDLE1, sub-IDLE modes
STOP mode
IDLE2, sub-IDLE modes
STOP mode
Address: FFFFF820H
0
Specification of operation in software standby mode
0
0
0
CHAPTER 25 STANDBY FUNCTION
PSM1
< >
PSM0
< >
Page 1222 of 1408
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