UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 461
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(c) Overflow operation
(d) Count value hold operation
(e) Counter read operation during count operation
(f) Underflow operation
The 16-bit counter overflows when it counts up from FFFFH to 0000H in the free-running mode, pulse width
measurement mode, and encoder compare mode. If the counter overflows in the free-running mode and pulse
width measurement mode, the TT0OPT0.TT0OVF bit is set to 1 and an interrupt request signal (INTTT0OV) is
generated.
If the counter overflows in the encoder compare mode, the TT0OPT1.TT0EOF bit is set to 1 and an interrupt
request signal (INTTT0OV) is generated.
Note that the INTTT0OV signal is not generated under the following conditions.
• Immediately after a count operation has been started
• If the counter value matches the compare value FFFFH and is cleared
• When FFFFH is captured and cleared to 0000H in the pulse width measurement mode
Caution After the overflow interrupt request signal (INTTT0OV) has been generated, be sure to check
The value of the 16-bit counter is held by the TT0CTL2.TT0ECC bit in the encoder compare mode. The value
of the 16-bit counter is reset to FFFFH when the TT0ECC bit = 0 and TT0CTL0.TT0CE bit = 0. When the
TT0CE bit is next set to 1, the set value of the TT0TCW register is transferred to the 16-bit counter and a count
operation is performed.
If the TT0ECC bit = 1 and TT0CE bit = 0, the value of the 16-bit counter is held. When the TT0CE bit is next
set to 1, the counter resumes the count operation from the held value.
The value of the 16-bit counter of TMT0 can be read by using the TT0CNT register during the count operation.
When the TT0CTL0.TT0CE bit = 1, the value of the 16-bit counter can be read by reading the TT0CNT register.
If the TT0CNT register is read when the TT0CTL2.TT0ECC bit = 0 and TT0CE bit = 0, however, it is 0000H.
The held value of the TT0CNT register is read if the register is read when the TT0ECC bit = 1 and TT0CE bit =
0.
A 16-bit counter underflow occurs at the timing when the 16-bit counter value changes from 0000H to FFFFH
in the encoder compare mode. When an underflow occurs, the TT0OPT1.TT0EUF bit is set to 1 and an
interrupt request signal (INTTT0OV) is generated.
that the overflow flag (TT0OVF, TT0EOF bits) is set to 1.
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Page 461 of 1408
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