UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1100

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(9) Bus bridge control register (BRG_CTL)
16
9
8
0
Bit position
After reset: 0000 0000H
data_wait_en Data Wait Enable
cnv_err
no_wait_en
cnv_err_en
BRG_CTL
Bit name
16-32 Bits Cycle Convert Error
This bit is set when an error occurs due to reception of an unexpected cycle during
conversion from 16 to 32 bits. This bit reports occurrence of the INTUSBH1 interrupt. This
bit will never be set unless the cnv_err_en bit is set to “1”.
The INTUSBH1 (PCI cycle error) interrupt is issued during debugging and is not used
during normal operation.
Sets forcible insertion of 1 wait (data wait) to the end of a CPU bus cycle.
No Wait Enable
Sets whether to enable no wait operation of a CPU bus cycle.
Before changing the value of this bit from “1” to “0”, it is recommended to read this bit once
and then write the value so as to make up the time lag until the change is reflected. The
read value at that time may not be correct because waits have not been inserted correctly,
so discard the read value.
16-32 Bits Cycle Convert Error Enable
This bit is used to set and clear interrupt sources. When it is set to “0”, the cnv_err bit is
cleared and masks the interrupt source at the same time.
The INTUSBH1 (PCI cycle error) interrupt is issued during debugging and is not used
during normal operation.
31
15
23
0
0
0
7
0
R/W
0: No interrupt source has occurred.
1: Cycle Convert Error detected.
0: Does not insert a data wait forcibly (initial value).
1: Forcibly inserts a data wait.
0: Disables no wait operation (at least 1 wait is always inserted) (initial value)
1: Enables wait operation (recommended)
0: Clears the interrupt source (initial value)
1: Enables the interrupt source.
Address: 002E1024H
30
22
14
0
0
0
6
0
29
21
13
5
0
0
0
0
28
12
20
0
0
0
4
0
CHAPTER 21 USB HOST CONTROLLER (USBH)
Function
27
19
11
0
0
0
3
0
26
18
10
0
0
0
0
2
data_
wait_en
25
17
0
0
9
1
0
cnv_err_en
no_
wait_en
cnv_err
24
16
0
8
0
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