UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1093

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(3) PCI control register 1 (PCI_CONTROL1)
31-24
16
9, 8
5
4
3
2
1
Bit position
PCI_CONTROL1
After reset: 0700 0300H
pci_parkcnt
[7:0]
pci_bpmode PCI Bus Parking Mode
pci_req_en
[1:0]
pci_pchken PCI Parity Check Enable
pci_reset
sram_en
sdram_en
mem_en
Bit name
PCI Bus Parking Timer
Sets the time required for shifting to Bus Parking mode. Counting starts by setting FRAME
and IRDY to “1”.
Use this field with the initial setting.
Only the V850ES/JG3-U and V850ES/JH3-U can serve as the bus parking master (initial
value).
The bus parking master is the master that accessed the PCI bus last.
Use this field with the initial setting.
PCI Request Enable
The pci_req_en0 bit is fixed to “1”.
Disable PCI requests (initial value).
Enables PCI requests.
Set this bit (1) when issuing a PCI request.
Disables parity check for PCI bus (initial value).
Enables parity check for PCI bus.
Use this field with the initial setting.
PCI Reset
The PCI bus is in the reset state (initial value).
The PCI bus is in the reset release state.
Set this bit (1) when accessing the OHCI host controller.
SRAM Area Enable
Does not respond to access from PCI bus to SRAM area (initial value).
Responds to access from PCI bus to SRAM area.
Set this bit (1) when accessing SRAM from the OHCI host controller.
SDRAM Area Enable
Does not respond to access from PCI bus to SDRAM area (initial value).
Responds to access from PCI bus to SDRAM area.
Set this bit (1) when accessing SDRAM from the OHCI host controller.
PCI Memory Area Enable
Disables access from CPU to PCI memory area (initial value).
Enables access from CPU to PCI memory area.
Set this bit (1) when accessing an OHCI host configuration register of the OHCI host
controller.
pci_
parkcnt7
31
15
23
0
0
7
0
R/W
pci_
parkcnt6
Address: 002E1008H
30
22
14
0
0
6
0
pci_pchken
pci_
parkcnt5
29
21
13
0
0
5
pci_reset
pci_
parkcnt4
12
28
20
4
0
0
CHAPTER 21 USB HOST CONTROLLER (USBH)
Function
pci_
parkcnt3
sram_en
27
19
11
0
0
3
sdram_en
pci_
parkcnt2
26
18
10
0
0
2
pci_
parkcnt1
mem_en
pci_req_
en1
25
17
0
9
1
pci_
parkcnt0
pci_req_
en0
pci_
bpmode
24
16
8
0
0
Page 1093 of 1408