UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1127

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
4
3
2
1
0
Bit position
UED
RDD
SFD
WDHD
SOD
Bit name
Unrecoverable Error Disable
Sets whether to remove UE from the interrupt sources.
When this bit is read, the value of the corresponding bit of the HcInterruptEnable register is
read. Writing “1” to this bit clears to 0 from the interrupt sources.
To set this bit to “1”, write “1” to the corresponding bit of the HcInterruptEnable register.
Resume Detected Disable
Sets whether to remove RD from the interrupt sources.
When this bit is read, the value of the corresponding bit of the HcInterruptEnable register is
read. Writing “1” to this bit clears RD from the interrupt sources.
To set this bit to “1”, write “1” to the corresponding bit of the HcInterruptEnable register.
StartOfFrame Disable
Sets removing of SF from interrupt sources.
When this bit is read, the value of the corresponding bit of the HcInterruptEnable register is
read. Writing “1” to this bit clears SF from the interrupt sources.
To set this bit to “1”, write “1” to the corresponding bit of the HcInterruptEnable register.
Writeback Done Head Disable
Sets whether to remove WDH from the interrupt sources.
When this bit is read, the value of the corresponding bit of the HcInterruptEnable register is
read. Writing “1” to this bit clears WDH from the interrupt sources.
To set this bit to “1”, write “1” to the corresponding bit of the HcInterruptEnable register.
Scheduling Overrun Disable
Sets whether to remove SO from interrupt sources.
When this bit is read, the value of the corresponding bit of the HcInterruptEnable register is
read. Writing “1” to this bit clears SO from the interrupt sources.
To set this bit to “1”, write “1” to the corresponding bit of the HcInterruptEnable register.
1: Disables UE as an interrupt source.
0: Ignored
1: Disables RD as an interrupt source.
0: Ignored
1: Disables SF as an interrupt source.
0: Ignored
1: Disables WDH as an interrupt source.
0: Ignored
1: Disables SO as an interrupt source.
0: Ignored
CHAPTER 21 USB HOST CONTROLLER (USBH)
Function
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