UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1090

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
21.5 Control Registers
21.5.1 USB control registers
21.6 PCI Host Bridge
21.6.1 PCI host bridge
with the following functions.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(1) USB clock select register (UCKSEL)
(2) USB function select register (UHCKMSK)
The PCI host bridge is a bridge circuit that connects to the CPU system to the OHCI host controller, and is equipped
• PCI master cycle control
• PCI slave cycle control
• PCI error handling
• PCI address conversion control
• Control of memory controller bus incorporated in V850ES/JG3-U and V850ES/JH3-U
• SRAM control
Controls the bus cycles by using hardware waits (WAIT) for the accesses from the CPU via the memory controller bus.
Issues the following PCI cycles in response to requests for bus access from the CPU (MEMC).
Acknowledges the PCI Memory Read/Write Cycle (up to 8 Dwords of burst transfer) in response to an access to the
SDRAM or SRAM area from the PCI bus.
Generates an error interrupt (INTUSBH0) upon Master Abort, Target Abort, PERR reception, and SERR reception.
(Holds the address immediately before the address at which an error occurs.)
The PCI window base address register, which is used to convert the physical addresses transferred from the CPU
and output them to the PCI bus, is available.
An 8 KB SRAM is incorporated as a shared memory. It is mainly used for allocating descriptors. Controls and
arbitrates accesses to the SRAM areas from the CPU (MEMC) and the PCI bus.
The UCKSEL register selects the operation clock of the USB controllers.
The UCKSEL register is also used by the USB function controller. For details, see 20.6.1 (1) USB clock selection
register (UCKSEL).
The UHCKMSK register selects the functions of the USB controllers.
The UHCKMSK register is also used by the USB function controller. For details, see 20.6.1 (3) USB function
selection register (UHCKMSK).
- PCI Configuration Register Read/Write Single Cycle
- PCI Memory Read/Write Single Cycle
CHAPTER 21 USB HOST CONTROLLER (USBH)
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