UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 448
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 448 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(8) TMT0 option register 0 (TT0OPT0)
The TT0OPT0 register is an 8-bit register that sets the capture/compare operation and detects overflows.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TT0OPT0
After reset: 00H
Cautions 1. Rewrite the TT0CCS1 and TT0CCS0 bits when the TT0CE bit = 0. (The
TT0CCS1
TT0CCS0
Set (1)
Reset (0)
The TT0CCS1 bit setting is valid only in the free-running timer mode.
The TT0CCS0 bit setting is valid only in the free-running timer mode.
• The TT0OVF bit is set to 1 when the 16-bit counter value overflows from FFFFH
• An overflow interrupt request signal (INTTT0OV) is generated when the TT0OVF
• The TT0OVF bit is not cleared to 0 even when the TT0OVF bit or the TT0OPT0
• Before clearing the TT0OVF bit to 0 after generation of the INTTT0OV signal, be
• The TT0OVF bit can be both read and written, but the TT0OVF bit cannot be set
to 0000H in the free-running timer mode or the pulse width measurement mode.
bit is set to 1. The INTTT0OV signal is not generated in modes other than the
free-running timer mode and the pulse width measurement mode.
register are read when the TT0OVF bit = 1.
sure to confirm (by reading) that the TT0OVF bit is set to 1.
to 1 by software. Writing 1 has no effect on the operation of TMT0.
0
1
0
1
7
0
TT0OVF
R/W
Selected as compare register
Selected as capture register (cleared by the TT0CTL0.TT0CE bit = 0)
Selected as compare register
Selected as capture register (cleared by the TT0CTL0.TT0CE bit = 0)
2. Be sure to set bits 1 to 3, 6, and 7 to “0”.
6
0
same value can be written when the TT0CE bit = 1.) If rewriting was
mistakenly performed, clear the TT0CE bit to 0 and then set these bits
again.
Address: FFFFF607H
TT0CCS1 TT0CCS0
Overflow occurred
0 written to TT0OVF bit or TT0CTL0.TT0CE bit = 0
TT0CCR1 register capture/compare selection
TT0CCR0 register capture/compare selection
5
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
TMT0 overflow detection flag
4
3
0
2
0
1
0
TT0OVF
<0>
Page 448 of 1408
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