UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1143

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
1
0
Bit position R/W
R
W
R
W
PES
SPE
CCS
CPE
Bit name
Port Enable Status
Indicates whether ports are enabled or disabled.
This bit cannot be set when the CSC bit has been cleared to 0 (no device
connected).
Ports enter the Enable state when port reset is completed.
This bit is automatically cleared (0) by hardware when an overcurrent state,
disconnect, power-off, or bubble error is detected.
Set Port Enable
Sets the PES bit to “1”.
Writing “0” to this bit is ignored.
Change the port status by setting the SPR bit. The OHCI host controller of the
V850ES/JG3-U and V850ES/JH3-U does not support enabling of ports by using this
bit because the USB Specification does not, although the OHCI Specification does.
Current Connect Status
Indicates the current connection status at a downstream port.
Clear Port Enable
Clears the CPE bit.
When “1” is written to this bit, ports enter the Disable state. Writing “0” to this bit is
ignored.
1: Ports are enabled.
0: Ports are disabled.
1: A device is connected.
0: No device is connected.
CHAPTER 21 USB HOST CONTROLLER (USBH)
Function
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