UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 623
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
[TAB1 operation]
<Q1> Write the TAB1CCR1 register.
<Q2> Rewrite the register at the transfer timing that is generated after the TAB1CCR1 register has been
<Q3> The registers are transferred all at once at the transfer timing.
<Q4> The transfer timing is also culled as the interrupts are culled.
[TAA4 operation]
<P1> Write the TAB1CCR1 register.
<P2> Rewrite the register at the transfer timing that is generated after the TAB1CCR1 register has been
<P3> The registers are transferred all at once at the transfer timing.
<P4> The transfer timing is also culled as the interrupts are culled.
Remark
rewritten.
rewritten.
INTTAB1CC0 signal
This is an example of the operation when the TAB1OPT1.TAB1ICE bit = 1, TAB1OPT1.TAB1IOE bit =
1, and TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0 bits = 00001.
INTTAB1OV signal
16-bit counter
16-bit counter
CCR0 buffer
CCR1 buffer
CCR2 buffer
CCR3 buffer
CCR0 buffer
CCR1 buffer
OPT1 buffer
TAB1CCR0
TAB1CCR1
TAB1CCR2
TAB1CCR3
TAA4CCR0
TAA4CCR1
TAB1OPT1
Transfer
Transfer
(TAB1)
(TAA4)
Figure 11-31. Basic Operation in Intermittent Batch Rewrite Mode
register
register
register
register
register
register
register
register
register
register
register
register
register
register
timing
timing
<Q1>&<P1>
<Q4>
<Q4>
<P4>
CHAPTER 11 MOTOR CONTROL FUNCTION
<Q2>
<P2>
<Q3>
<Q3>
<Q3>
<Q3>
<Q3>
<P3>
<P3>
<Q4>
<Q4>
<P4>
Page 623 of 1408
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