UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 372

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UPD70F3763GC-UEU-AX

Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet

Specifications of UPD70F3763GC-UEU-AX

Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
TABnIOC2
(d) TABn I/O control register 2 (TABnIOC2)
(e) TABn counter read buffer register (TABnCNT)
(f) TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
The value of the 16-bit counter can be read by reading the TABnCNT register.
If D
to the TABnCCR3 register, the cycle and active level of the PWM waveform are as follows.
Remarks 1. TABn I/O control register 1 (TABnIOC1) and TABn option register 0 (TABnOPT0) are not
Cycle = (D
TOABn1 pin PWM waveform active level width = D
TOABn2 pin PWM waveform active level width = D
TOABn3 pin PWM waveform active level width = D
0
is set to the TABnCCR0 register, D
0
Figure 8-18. Setting of Registers in External Trigger Pulse Output Mode (3/3)
2. Updating TABn capture/compare register 2 (TABnCCR2) and TABn capture/compare register 3
3. n = 0, 1
0
+ 1) × Count clock cycle
used in the external trigger pulse output mode.
(TABnCCR3) is enabled by writing TABn capture/compare register 1 (TABnCCR1).
0
0
0
1
TABnEES1
to the TABnCCR1 register, D
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
0/1
TABnEES0
1
2
3
0/1
× Count clock cycle
× Count clock cycle
× Count clock cycle
TABnETS1 TABnETS0
0/1
2
to the TABnCCR2 register, and D
0/1
Select valid edge of
external trigger input
Select valid edge of
external event count input
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