UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 249

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(e) TAAn counter read buffer register (TAAnCNT)
(f) TAAn capture/compare register 0 (TAAnCCR0)
(g) TAAn capture/compare register 1 (TAAnCCR1)
The count value of the 16-bit counter can be read by reading the TAAnCNT register.
If D
signal (INTTAAnCC0) is generated when the number of external event counts reaches (D
Usually, the TAAnCCR1 register is not used in the external event count mode. However, the set value of
the TAAnCCR1 register is transferred to the CCR1 buffer register. When the count value of the 16-bit
counter matches the value of the CCR1 buffer register, a compare match interrupt request signal
(INTTAAnCC1) is generated.
Therefore, mask the interrupt signal by using the interrupt mask flag (TAAnCCMK1).
Caution When an external clock is used as the count clock, the external clock can be input only
Remarks 1. TAAn I/O control register 1 (TAAnIOC1) and TAAn option register 0 (TAAnOPT0) are not
0
is set to the TAAnCCR0 register, the counter is cleared and a compare match interrupt request
Figure 7-16. Register Setting for Operation in External Event Count Mode (2/2)
from the TIAAn0 pin. At this time, set the TAAnIOC1.TAAnIS1 and TAAnIOC1.TAAnIS0
bits to 00 (capture trigger input (TIAAn0 pin): no edge detection).
2. n = 0 to 3, 5
used in the external event count mode.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
0
+ 1).
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