DF2317VTE25 Renesas Electronics America, DF2317VTE25 Datasheet - Page 954
![MCU 3V 128K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2317VTE25
Manufacturer Part Number
DF2317VTE25
Description
MCU 3V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.D12312SVTE25V.pdf
(1146 pages)
Specifications of DF2317VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
79
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2317VTE25
HD64F2317VTE25
HD64F2317VTE25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2317VTE25V
Manufacturer:
AD
Quantity:
3 643
Company:
Part Number:
DF2317VTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Appendix A Instruction Set
A.5
Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See
table A.4 for the number of states per cycle.
How to Read the Table:
Legend:
R:B
R:W
W:B
W:W
:M
2nd
3rd
4th
5th
NEXT
EA
VEC
Rev.7.00 Feb. 14, 2007 page 920 of 1108
REJ09B0089-0700
JMP@aa:24
Instruction
Bus States during Instruction Execution
Byte-size read
Word-size read
Byte-size write
Word-size write
Transfer of the bus is not performed immediately after this cycle
Address of 2nd word (3rd and 4th bytes)
Address of 3rd word (5th and 6th bytes)
Address of 4th word (7th and 8th bytes)
Address of 5th word (9th and 10th bytes)
Address of next instruction
Effective address
Vector address
R:W 2nd
1
Internal operation,
1 state
2
R:W EA
3
4
Order of execution
End of instruction
Read effective address (word-size read)
No read or write
Read 2nd word of current instruction
(word-size read)
5
6
7
8
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