DF2317VTE25 Renesas Electronics America, DF2317VTE25 Datasheet - Page 1047

• Manufacturer Part Number: DF2317VTE25
• Description: MCU 3V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2317VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2317VTE25; HD64F2317VTE25

SMR0—Serial Mode Register 0
Bit
Initial value
Read/Write
Note: etu (Elementary Time Unit): Time for transfer of 1 bit
GSM Mode
0
1
Normal smart card interface mode operation
· TEND flag generated 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit
· Clock output on/off control only
GSM mode smart card interface mode operation
· TEND flag generated 11.0 etu after beginning of start bit
· Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control
:
:
:
R/W
GM
7
0
Block Transfer Mode Select
R/W
BLK
0
1
6
0
Normal smart card interface mode
Block transfer mode
Parity Enable
(Set to 1 when using the smart card interface)
R/W
PE
0
1
5
0
Setting prohibited
Parity bit addition and checking enabled
Notes:
Parity Mode
0
1
R/W
O/E
4
0
Even parity
Odd parity
1. When even parity is selected, the parity bit added to
2. When odd parity is selected, the parity bit added to
transmit data makes an even number of 1s in the
transmitted character and parity bit combined. Receive
data must have an even number of 1s in the received
character and parity bit combined.
transmit data makes an odd number of 1s in the
transmitted character and parity bit combined. Receive
data must have an odd number of 1s in the received
character and parity bit combined.
BCP1
R/W
3
0
Base Clock Pulse
BCP1 BCP0
*2
Rev.7.00 Feb. 14, 2007 page 1013 of 1108
*1
0
1
H'FF78
BCP0
R/W
2
0
0
1
0
1
Clock Select
Appendix B Internal I/O Registers
0
1
32 clocks
64 clocks
372 clocks
256 clocks
CKS1
Base Clock Pulse
R/W
1
0
0
1
0
1
φ clock
φ/4 clock
φ/16 clock
φ/64 clock
CKS0
R/W
Smart Card Interface 0
0
0
REJ09B0089-0700