DF2317VTE25 Renesas Electronics America, DF2317VTE25 Datasheet - Page 1059
![MCU 3V 128K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2317VTE25
Manufacturer Part Number
DF2317VTE25
Description
MCU 3V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.D12312SVTE25V.pdf
(1146 pages)
Specifications of DF2317VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
79
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2317VTE25
HD64F2317VTE25
HD64F2317VTE25
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SCR1—Serial Control Register 1
Bit
Initial value
Read/Write
:
:
:
Note: * TXI interrupt requests can be cleared by reading 1 from the
Transmit Interrupt Enable
R/W
TIE
0
1
7
0
Transmit-data-empty interrupt (TXI) request disabled *
Transmit-data-empty interrupt (TXI) request enabled
TDRE flag, then clearing it to 0, or by clearing the TIE bit to 0.
Receive Interrupt Enable
Note: * RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF, FER, PER, or
R/W
RIE
0
1
6
0
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request disabled
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request enabled
Transmit Enable
Notes: 1. The TDRE flag in SSR is fixed at 1.
ORER flag, then clearing the flag to 0, or by clearing the RIE bit to 0.
0
1
R/W
TE
Transmission disabled *
Transmission enabled *
5
0
2. In this state, serial transmission is started when transmit data is written to TDR and the
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transmit format before setting the TE bit to 1.
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain
Receive Enable
0
1
R/W
RE
Reception disabled *
Reception enabled *
4
0
2. Serial reception is started in this state when a start bit is detected in asynchronous mode or
their states.
serial clock input is detected in synchronous mode.
SMR setting must be performed to decide the receive format before setting the RE bit to 1.
Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR,
Multiprocessor Interrupt Enable
0
1
MPIE
R/W
3
0
2
1
Multiprocessor interrupts disabled
[Clearing conditions]
· When the MPIE bit is cleared to 0
· When data with MPB = 1 is received
Multiprocessor interrupts enabled *
Receive-data-full interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor
bit set to 1 is received
receive error detection, and setting of the RDRF, FER, and ORER flags in SSR, is not
performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to
1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts
(when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled.
Transmit End Interrupt Enable
Note: * TEI clearing can be performed by reading 1 from the TDRE flag in SSR, then
0
1
2
TEIE
1
R/W
2
0
Transmit-end interrupt (TEI) request disabled *
Transmit-end interrupt (TEI) request enabled *
clearing it to 0 and clearing the TEND flag to 0, or by clearing the TEIE bit to 0.
Clock Enable
SMCR
SMIF
CKE1
R/W
0
1
1
1
1
1
1
1
0
Rev.7.00 Feb. 14, 2007 page 1025 of 1108
H'FF82
SMR
GM
CKE0
0
0
1
1
1
1
R/W
0
0
CKE1
Appendix B Internal I/O Registers
SCR setting
0
0
0
0
1
1
See SCI specification
CKE0
0
1
0
1
0
1
Smart Card Interface 1
Operates as port I/O pin
Clock output as SCK output pin
Fixed-low output as SCK output pin
Clock output as SCK output pin
Fixed-high output as SCK output pin
Clock output as SCK output pin
SCK pin function
REJ09B0089-0700
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