DF2317VTE25 Renesas Electronics America, DF2317VTE25 Datasheet - Page 1089
![MCU 3V 128K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2317VTE25
Manufacturer Part Number
DF2317VTE25
Description
MCU 3V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.D12312SVTE25V.pdf
(1146 pages)
Specifications of DF2317VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
79
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2317VTE25
HD64F2317VTE25
HD64F2317VTE25
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TSR0—Timer Status Register 0
Bit
Initial value
Read/Write
Note: * Can only be written with 0 for flag clearing.
:
:
:
⎯
⎯
7
1
⎯
⎯
6
1
⎯
⎯
5
0
Overflow Flag
R/(W)*
TCFV
0
1
4
0
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
R/(W)*
Input Capture/Output Compare Flag D
TGFD
0
1
3
0
[Clearing conditions]
• When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC
• When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
• When TCNT = TGRD while TGRD is functioning as output compare register
• When TCNT value is transferred to TGRD by input capture signal while
Input Capture/Output Compare Flag C
is 0
TGRD is functioning as input capture register
0
1
R/(W)*
TGFC
2
0
[Clearing conditions]
• When DTC is activated by TGIC interrupt while DISEL bit of MRB in
• When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
• When TCNT = TGRC while TGRC is functioning as output compare
• When TCNT value is transferred to TGRC by input capture signal
DTC is 0
register
while TGRC is functioning as input capture register
R/(W)*
Input Capture/Output Compare Flag B
TGFB
0
1
1
0
Rev.7.00 Feb. 14, 2007 page 1055 of 1108
[Clearing conditions]
• When DTC is activated by TGIB interrupt while DISEL bit
• When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
• When TCNT = TGRB while TGRB is functioning as
• When TCNT value is transferred to TGRB by input
of MRB in DTC is 0
output compare register
capture signal while TGRB is functioning as input capture
register
R/(W)*
Input Capture/Output Compare Flag A
TGFA
0
1
0
0
H'FFD5
[Clearing conditions]
• When DTC is activated by TGIA interrupt while
• When 0 is written to TGFA after reading
[Setting conditions]
• When TCNT = TGRA while TGRA is functioning
• When TCNT value is transferred to TGRA by
Appendix B Internal I/O Registers
DISEL bit of MRB in DTC is 0
TGFA = 1
as output compare register
input capture signal while TGRA is functioning
as input capture register
REJ09B0089-0700
TPU0
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