DF2317VTE25 Renesas Electronics America, DF2317VTE25 Datasheet - Page 225
![MCU 3V 128K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2317VTE25
Manufacturer Part Number
DF2317VTE25
Description
MCU 3V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.D12312SVTE25V.pdf
(1146 pages)
Specifications of DF2317VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
79
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2317VTE25
HD64F2317VTE25
HD64F2317VTE25
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Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn
0
1
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 7.5, together with the vector numbers
generated by the interrupt controller.
For DTCE bit setting, read/write operations must be performed using bit-manipulation instructions
such as BSET and BCLR. For the initial setting only, however, when multiple activation sources
are set at one time, it is possible to disable interrupts and write after executing a dummy read on
the relevant register.
7.2.8
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Note: * Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0.
Bit
Initial value :
R/W
DTC Vector Register (DTVECR)
Description
DTC activation by this interrupt is disabled
[Clearing conditions]
•
•
DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
:
:
When the DISEL bit is 1 and the data transfer has ended
When the specified number of transfers have ended
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
R/(W)
7
0
R/(W) *
6
0
R/(W) *
5
0
R/(W) *
4
0
Rev.7.00 Feb. 14, 2007 page 191 of 1108
R/(W) *
3
0
Section 7 Data Transfer Controller
R/(W) *
2
0
REJ09B0089-0700
R/(W) *
1
0
(Initial value)
(n = 7 to 0)
R/(W) *
0
0
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