DF2317VTE25 Renesas Electronics America, DF2317VTE25 Datasheet - Page 294
![MCU 3V 128K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2317VTE25
Manufacturer Part Number
DF2317VTE25
Description
MCU 3V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.D12312SVTE25V.pdf
(1146 pages)
Specifications of DF2317VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
79
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2317VTE25
HD64F2317VTE25
HD64F2317VTE25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2317VTE25V
Manufacturer:
AD
Quantity:
3 643
Company:
Part Number:
DF2317VTE25V
Manufacturer:
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Quantity:
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Section 8 I/O Ports
8.7.2
Table 8.11 shows the port B register configuration.
Table 8.11 Port B Registers
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
• Modes 4 and 5
• Mode 6 *
• Mode 7 *
Note: * Modes 6 and 7 are not available in the ROMless versions.
Rev.7.00 Feb. 14, 2007 page 260 of 1108
REJ09B0089-0700
Bit
Initial value :
R/W
The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits.
Setting PBDDR bits to 1 makes the corresponding port B pins address outputs, while clearing
the bits to 0 makes the pins input ports.
Setting PBDDR bits to 1 makes the corresponding port B pins outputs, while clearing the bits
to 0 makes the pins input ports.
Register Configuration
:
:
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
W
7
0
W
6
0
Abbreviation
PBDDR
PBDR
PBPCR
PORTB
W
5
0
W
4
0
R/W
W
R/W
R
R/W
W
3
0
H'00
Initial Value
H'00
Undefined
H'00
W
2
0
W
1
0
Address *
H'FEBA
H'FF6A
H'FF5A
H'FF71
W
0
0
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