DF2317VTE25 Renesas Electronics America, DF2317VTE25 Datasheet - Page 1055

• Manufacturer Part Number: DF2317VTE25
• Description: MCU 3V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2317VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2317VTE25; HD64F2317VTE25

SMR1—Serial Mode Register 1
Bit
Initial value
Read/Write
:
:
:
Asynchronous Mode/Synchronous Mode Select
R/W
C/A
0
1
7
0
Asynchronous mode
Synchronous mode
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
Character Length
CHR
R/W
0
1
6
0
8-bit data
7-bit data*
With 7-bit data, it is not possible to select LSB-first or MSB-first transfer.
Note:
R/W
Parity Enable
PE
5
0
0
1
* When the PE bit is set to 1, the parity (even or odd) specified by
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
the O/E bit is added to transmit data before transmission. In
reception, the parity bit is checked for the parity (even or odd)
specified by the O/E bit.
R/W
Parity Mode
O/E
Notes:
4
0
0
1
Even parity
Odd parity
1. When even parity is selected, the parity bit added to
2. When odd parity is selected, the parity bit added to
STOP
Stop Bit Length
R/W
0
1
3
0
transmit data makes an even number of 1s in the
transmitted character and parity bit combined. Receive
data must have an even number of 1s in the received
character and parity bit combined.
transmit data makes an odd number of 1s in the
transmitted character and parity bit combined. Receive
data must have an odd number of 1s in the received
character and parity bit combined.
H'FF80
1 stop bit
2 stop bits
Rev.7.00 Feb. 14, 2007 page 1021 of 1108
*2
*1
Multiprocessor Mode
R/W
MP
0
1
2
0
Multiprocessor function
disabled
Multiprocessor format
selected
Clock Select
Appendix B Internal I/O Registers
0
1
CKS1
R/W
1
0
0
1
0
1
φ clock
φ/4 clock
φ/16 clock
φ/64 clock
CKS0
R/W
0
0
REJ09B0089-0700
SCI1