DF2317VTE25 Renesas Electronics America, DF2317VTE25 Datasheet - Page 346

• Manufacturer Part Number: DF2317VTE25
• Description: MCU 3V 128K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2317VTE25

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2317VTE25; HD64F2317VTE25

Section 9 16-Bit Timer Pulse Unit (TPU)
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge.
When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both
edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is
ignored and the phase counting mode setting has priority.
Bit 4
CKEG1
0
1
Note: Internal clock edge selection is valid when the input clock is φ/4 or slower. This setting is
Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter
clock. The clock source can be selected independently for each channel. Table 9.4 shows the clock
sources that can be set for each channel.
Table 9.4
Channel φ/1
0
1
2
3
4
5
Legend:
Blank: No setting
Rev.7.00 Feb. 14, 2007 page 312 of 1108
REJ09B0089-0700
:
ignored if the input clock is φ/1, or when overflow/underflow of another channel is selected.
Setting
Bit 3
CKEG0
0
1
—
TPU Clock Sources
φ/4
φ/16 φ/64 φ/256 φ/1024 φ/4096
Internal Clock
Description
Count at rising edge
Count at falling edge
Count at both edges
TCLKA TCLKB TCLKC TCLKD
External Clock
(Initial value)
Overflow/
Underflow
on Another
Channel