DF2317VTE25 Renesas Electronics America, DF2317VTE25 Datasheet - Page 646
![MCU 3V 128K 100-TQFP](/photos/28/61/286108/100-tqfp_sml.jpg)
DF2317VTE25
Manufacturer Part Number
DF2317VTE25
Description
MCU 3V 128K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.D12312SVTE25V.pdf
(1146 pages)
Specifications of DF2317VTE25
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
79
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2317VTE25
HD64F2317VTE25
HD64F2317VTE25
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2317VTE25V
Manufacturer:
AD
Quantity:
3 643
Company:
Part Number:
DF2317VTE25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 17 ROM
Table 17.14 Settings for Each Operating Mode in Programmer Mode
Mode
Read
Output disable
Command write
Chip disable *
Legend:
H:
L:
Hi-Z: High impedance
×:
Notes: 1. Chip disable is not a standby state; internally, it is an operation state.
Table 17.15 Programmer Mode Commands
Command Name
Memory read mode
Auto-program mode
Auto-erase mode
Status read mode
Legend:
RA: Read address
PA: Program address
×:
Notes: 1. In auto-program mode, 129 cycles are required for command writing by a simultaneous
Rev.7.00 Feb. 14, 2007 page 612 of 1108
REJ09B0089-0700
Don’t care
High level
Low level
Don’t care
2. Ain indicates that there is also address input in auto-program mode.
3. For command writes when making a transition to auto-program or auto-erase mode,
2. In memory read mode, the number of cycles depends on the number of address write
input a high level to the FWE pin.
128-byte write.
cycles (n).
1
FWE
H or L
H or L
H or L *
H or L
1 + n
129
2
2
Number
of Cycles
3
CE
L
L
L
H
Write
Write
Write
Write
Mode
OE
L
H
H
×
×
×
×
×
1st Cycle
Address Data
Pin Names
WE
H
H
L
×
H'00
H'40
H'20
H'71
Read
Write
Write
Write
Mode
I/O
Data output
Hi-Z
Data input
Hi-Z
7
to I/O
2nd Cycle
RA
PA
×
×
Address Data
0
A
Ain
×
Ain *
×
18
to A
2
Dout
Din
H'20
H'71
0
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