QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 91

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Host Bridge Device 0 - Configuration Registers (D0:F0)
Datasheet
25:3
2:1
Bit
27
26
0
Access
R/W/L
R/W/L
R/W/L
R/W/L
RO
000000h
Default
Value
00b
0b
0b
0b
128-MB Address Mask:
This bit is either part of the PCI Express Base Address (R/W) or
part of the Address Mask (RO, read 0b), depending on the value
of bits 2:1 in this register.
64-MB Base Address Mask:
This bit is either part of the PCI Express Base Address (R/W) or
part of the Address Mask (RO, read 0b), depending on the value
of bits 2:1 in this register.
Reserved
Length:
This field describes the length of this region - Enhanced
Configuration Space Region/Buses Decoded
00: 256 MB (Buses 0-255). Bits 31:28 are decoded in the PCI
Express Base Address field.
01: 128 MB (Buses 0-127). Bits 31:27 are decoded in the PCI
Express Base Address field.
10: 64 MB (Buses 0-63). Bits 31:26 are decoded in the PCI
Express Base Address field.
11: Reserved
PCIEXBAR Enable (PCIEXBAREN):
0: PCIEXBAR register is disabled. Memories read and write
transactions proceed as if there were no PCIEXBAR register.
PCIEXBAR register bits 31:28 are R/W with no functionality
behind them.
1: The PCIEXBAR register is enabled. Memories read and write
transactions whose address bits 31:28 match PCIEXBAR 31:28
will be translated to configuration reads and writes within the
(G)MCH. These translation cycles are routed as shown in the
tables above.
(Sheet 2 of 2)
Description
91