QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 122

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.2.10
6.2.11
122
C0DRA2 - Channel 0 DRAM Rank 2,3 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
C0DCLKDIS - Channel 0 DRAM Clock Disable
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register can be used to disable the System Memory Clock signals to each SO-DIMM
slot, which can significantly reduce EMI and Power concerns for clocks that go to
unpopulated SO-DIMMs. Clocks should be enabled based on whether or not a slot is
populated.
Since there are multiple clock signals assigned to each rank of a DIMM, it is important
to clarify exactly which rank width field affects which clock signal.
7:7
6:4
3:3
2:0
Bit
Access
R/W
R/W
RO
RO
Default
Value
000b
000b
0b
0b
Reserved
Channel 0 DRAM Odd Rank Attribute:
This 3-bit field defines the page size of the corresponding rank.
000: Unpopulated
001: Reserved
010: 4 KB
011: 8 KB
100: 16 KB
Others: Reserved
Reserved
Channel 0 DRAM Even Rank Attribute:
This 3-bit field defines the page size of the corresponding rank.
000: Unpopulated
001: Reserved
010: 4 KB
011: 8 KB
100: 16 KB
Others: Reserved
0/0/0/MCHBAR
109h
00h
R/W; RO
8 bits
0/0/0/MCHBAR
10Ch
00h
R/W; RO
8 bits
Description
Device 0 Memory Mapped I/O Register
Datasheet