QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 357

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Functional Description
10.3.1.2
10.3.1.3
10.3.1.4
10.3.1.5
Figure 16.
Datasheet
Transaction Layer
The upper layer of the PCI Express architecture is the transaction layer. The transaction
layer’s primary responsibility is the assembly and disassembly of transaction layer
packets (TLPs). TLPs are used to communicate transactions, such as read and write, as
well as certain types of events. The transaction layer also manages flow control of TLPs.
Data Link Layer
The middle layer in the PCI Express stack, the data link layer, serves as an intermediate
stage between the transaction layer and the physical layer. Responsibilities of data link
layer include link management, error detection, and error correction.
Physical Layer
The physical layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry.
PCI Express Configuration Mechanism
The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
PCI Express Related Register Structures in (G)MCH
PCI Express extends the configuration space to 4096 bytes per device/function as
compared to 256 bytes allowed by the current PCI Local Bus Specification. PCI Express
configuration space is divided into a conventional PCI 2.3 compatible region, which
consists of the first 256 bytes of a logical device’s configuration space and an extended
PCI Express region which consists of the remaining configuration space. The
conventional PCI 2.3 compatible region can be accessed using either the mechanisms
defined in the current PCI Local Bus Specification, or using the enhanced PCI Express
configuration access mechanism described in the PCI Express Enhanced Configuration
Mechanism section of the PCI Express* Base Specification.
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