QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 355

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Functional Description
10.2.8.1
10.2.8.2
10.2.8.3
Datasheet
Self Refresh Entry and Exit Operation
When entering the Suspend-To-RAM (STR) state, (G)MCH will flush pending cycles and
then enter all SDRAM ranks into self refresh. In STR, the CKE signals remain LOW so
the SDRAM devices will perform self-refresh.
Dynamic Rank Power Down Operation
The Mobile Intel 945GM/GME/PM/GMS/GU/GSE, 943/940GML and Intel 945GT Express
Chipsets implement aggressive CKE control to dynamically put the DRAM devices in a
power down state. The (G)MCH controller can be configured to put the devices in active
power down (CKE deassertion with open pages) or precharge power down (CKE
deassertion with all pages closed). Precharge power down provides greater power
savings but has a bigger performance impact, since all pages are needed to be closed
before putting the devices in power down mode.
If dynamic power down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
DRAM I/O Power Management
(G)MCH implements several power saving features where different groups of IO buffers
are disabled when safe to do so in a dynamic fashion thereby saving IO power. These
features are listed below.
• SO-DIMM clock gating disable – The Mobile Intel 945GM/GME/PM/GMS/GSE, 943/
• Address and control tri-state enable – If CKE for any given rank is deasserted, the
• Data sense amp disable (self refresh, dynamic) - When all the SDRAM ranks have
• Output only sense amp disable – Sense amplifiers of all IO buffers which are
940GML and Intel 945GT Express Chipsets have 2 clock pairs per SO-DIMM. If only
one SO-DIMM is populated, it allows the other 2 clock pairs to be disabled.
CS# to that rank is disabled. If all CKEs are deasserted (such as in S3), All address
and control buffers (excluding CKEs) are disabled.
been put in a self refresh state, or during normal operation, if no memory accesses
are pending, the sense amplifiers for all data buffers are turned off.
functionally outputs only (everything except DQ and DQS) are turned off.
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