QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 384

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

10.6.4
10.6.4.1
10.6.4.1.1
10.6.4.1.2
10.6.4.2
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Power Management Overview
Dynamic Power Management on I/O
(G)MCH provides several features to reduce I/O power dynamically.
System Memory
PCI Express
System Memory Power Management
The main memory is power managed during normal operation and in low power ACPI
Cx states.
Each row has a separate CKE (clock enable) pin that is used for power management.
dynamic rank power down is employed during normal operation. Based on idle
conditions to a given row of memory that memory row may be powered down. If the
pages for a row have all been closed at the time of power down, then the device will
enter the active power down state. If pages remain open at the time of power down the
devices will enter the precharge power down state.
Disabling Unused System Memory Outputs
Any System Memory interface signal that goes to a SO-DIMM connector in which it is
not connected to any actual memory devices (such as SO-DIMM connector is
unpopulated, or is single-sided) will be tri-stated.
The benefits of disabling unused SM signals are:
When a given row is not populated (as determined by the DRAM rank boundary register
values) then the corresponding chip select and SCKE signals will not be driven.
SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
Dynamic Row Power Management
Dynamic row power-down is employed during normal operation. Based on idle
conditions, a given memory row may be powered down. If the pages for a row have all
been closed at the time of power down, then the device will enter the precharge power-
down state. If pages remain open at the time of power-down the devices will enter the
active power-down state.
• dynamic rank power down
• Conditional memory self-refresh based on CPU state, PCI Express link states, and
• Dynamic ODT disable when MCH is driving
• DPWR# signal to disable CPU sense amps when no read return data pending
• Active power management support using L0, L0s, and L1 states
• All inputs and outputs disabled in L2/L3 Ready state
• Reduce Power Consumption
• Reduce possible overshoot/undershoot signal quality issues seen by the (G)MCH
graphics/display activity
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
Functional Description
Datasheet