QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 266

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

7.2.5
7.2.6
266
VC0RCAP - VC0 Resource Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
VC0RCTL - VC0 Resource Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Controls the resources associated with PCI Express Virtual Channel 0.
31:16
15:15
30:27
26:24
14:0
23:8
7:1
Bit
Bit
31
0
Access
Access
R/W
RO
RO
RO
RO
RO
RO
RO
RO
Default
Default
Value
0000h
Value
0000h
000b
00h
7Fh
0b
1b
0h
1b
Reserved
Reject Snoop Transactions (RSNPT):
TLP header are allowed on this VC.
header will be rejected as an Unsupported Request.
Reserved
VC0 Enable (VC0E):
For VC0 this is hardwired to 1 and read only as VC0 can never be
disabled.
Reserved
VC0 ID (VC0ID):
Assigns a VC ID to the VC resource. For VC0 this is hardwired to 0
and read only.
Reserved
TC/VC0 Map (TCVC0M):
Indicates the TCs (Traffic Classes) that are mapped to the VC
resource.
Bit locations within this field correspond to TC values. For
example, when bit 7 is set in this field, TC7 is mapped to this VC
resource. When more than one bit in this field is set, it indicates
that multiple TCs are mapped to the VC resource. In order to
remove one or more TCs from the TC/VC Map of an enabled VC,
software must ensure that no new or outstanding transactions
with the TC labels are targeted at the given Link.
TC0/VC0 Map (TC0VC0M):
Traffic Class 0 is always routed to VC0.
0: Transactions with or without the No Snoop bit set within the
1: Any transaction without the No Snoop bit set within the TLP
PCI Express Graphics Device 1 Configuration Registers (D1:F0)
0/1/0/MMR
110-113h
00000000h
RO
32 bits
0/1/0/MMR
114-117h
800000FFh
R/W; RO
32 bits
Description
Description
Datasheet