QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 121

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Device 0 Memory Mapped I/O Register
6.2.9
Datasheet
C0DRA0 - Channel 0 DRAM Rank 0,1 Attribute
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The DRAM rank attribute registers define the page sizes to be used when accessing
different ranks. These registers should be left with their default value (all 0’s) for any
rank that is unpopulated, as determined by the corresponding CxDRB registers. Each
byte of information in the CxDRA registers describes the page size of a pair of ranks.
Channel and Rank Map:
Ch0 Rank 0,1:
Ch0 Rank 2,3:
7:7
6:4
3:3
2:0
Bit
Access
R/W
R/W
RO
RO
108h
109h
Default
Value
000b
000b
0b
0b
Reserved
Channel 0 DRAM Odd Rank Attribute:
This 3-bit field defines the page size of the corresponding rank.
000: Unpopulated
001: Reserved
010: 4 KB
011: 8 KB
100: 16 KB
Others: Reserved
Reserved
Channel 0 DRAM Even Rank Attribute:
This 3-bit field defines the page size of the corresponding rank.
000: Unpopulated
001: Reserved
010: 4 KB
011: 8 KB
100: 16 KB
Others: Reserved
0/0/0/MCHBAR
108h
00h
R/W; RO
8 bits
Description
121