QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 338

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QG82945GSE S LB2R

Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
10.1.6
10.1.7
338
FSB Interrupt Overview
The Intel Core Duo and Intel Core Solo processor supports FSB interrupt delivery. They
do not support the APIC serial bus interrupt delivery mechanism. Interrupt related
messages are encoded on the FSB as “Interrupt Message Transactions”. FSB interrupts
may originate from the CPUs on the FSB, or from a downstream device on the DMI or
PCI Express Graphics Attach. In the later case, the (G)MCH drives the “Interrupt
Message Transaction” on the FSB.
In the IOxAPIC environment, an interrupt is generated from the IOxAPIC to a CPU in
the form of an upstream Memory Write. The ICH contains IOxAPICs, and its interrupts
are generated as upstream DMI Memory Writes. Furthermore, the PCI Local Bus
Specification and PCI Express* Base Specification define MSI’s (Message Signaled
Interrupts) that are also in the form of Memory Writes. A PCI device may generate an
interrupt as an MSI cycle on its PCI bus instead of asserting a hardware signal to the
IOxAPIC. The MSI may be directed to the IOxAPIC. The IOxAPIC in turn generates an
interrupt as an upstream DMI Memory Write. Alternatively, the MSI may directly route
to the FSB. The target of an MSI is dependent on the address of the interrupt Memory
Write. The (G)MCH forwards upstream DMI and PCI Express Graphics Attach low
priority Memory Writes to address 0FEEx_xxxxh to the FSB as “Interrupt Message
Transactions”.
The (G)MCH also broadcasts EOI cycles generated by a CPU downstream to the PCI
Express Port and DMI interfaces.
APIC Cluster Mode Support
This is required for backwards compatibility with existing software, including various
OS’s. As one example, beginning with Microsoft Windows* 2000 there is a mode
(boot.ini) that allows an end user to enable the use of cluster addressing support of the
APIC.
Functional Description
Datasheet

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