QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 265

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

PCI Express Graphics Device 1 Configuration Registers (D1:F0)
7.2.3
7.2.4
Datasheet
PVCCAP2 - Port VC Capability Register 2
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register describes the configuration of PCI Express Virtual Channels associated
with this port.
PVCCTL - Port VC Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:24
23:8
15:4
7:0
3:1
Bit
Bit
0
Access
Access
R/W
RO
RO
RO
RO
RO
Default
Default
0000h
Value
Value
000h
000b
00h
01h
0b
VC Arbitration Table Offset (VCATO):
Indicates the location of the VC Arbitration Table.
This field contains the zero-based offset of the table in
DQWORDS (16 bytes) from the base address of the Virtual
Channel Capability Structure. A value of 0 indicates that the table
is not present (due to fixed VC priority).
Reserved
VC Arbitration Capability (VCAC):
Indicates that the only possible VC arbitration scheme is
hardware fixed (in the root complex).
VC1 is the highest priority.
VC0 is the lowest priority.
Reserved
VC Arbitration Select (VCAS):
This field will be programmed by software to the only possible
value as indicated in the VC Arbitration Capability field. The value
001b when written to this field will indicate the VC arbitration
scheme is hardware fixed (in the root complex).
This field can not be modified when more than one VC in the
LPVC group is enabled.
Reserved
0/1/0/MMR
108-10Bh
00000001h
RO
32 bits
0/1/0/MMR
10C-10Dh
0000h
R/W; RO
16 bits
Description
Description
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