QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 224

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

6.7.16
6.7.17
224
EPLE2A - EP Link Entry 2 Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is the second part of a Link Entry which declares an internal link to
another Root Complex Element.
PORTARB - Port Arbitration Table
B/D/F/Type:
Address Offset:
Default Value
Access:
Size:
The port arbitration table register is a read-write register array used to store the
arbitration table for Port Arbitration of the Egress Port VC resource.
63:28
27:20
19:15
14:12
11:0
Bit
Access
RO
RO
RO
RO
RO
0000000
Default
00001b
Value
000b
000h
00h
00h
Reserved
Bus Number (BUSN):
Device Number (DEVN):
Target for this link is PCI Express x16 port (Device 1).
Function Number (FUNN):
Reserved
§
0/0/0/EPBAR
68-6Fh
0000000000008000h
RO
64 bits
0/0/0/EPBAR
100-11Fh
: 000000000000000000000000000000000
000000000000000000000000000000h
R/W
256 bits
Description
Device 0 Memory Mapped I/O Register
Datasheet