QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 205

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QG82945GSE S LB2R

Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
Device 0 Memory Mapped I/O Register
6.6.8
Datasheet
DMIVC1RCAP - DMI VC1 Resource Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:24
23:23
22:16
15:15
14:8
7:0
Bit
Access
RO
RO
RO
RO
RO
RO
Default
Value
00h
00h
00h
01h
0b
1b
Reserved
Reserved
Reserved
Reject Snoop Transactions (REJSNPT):
the TLP header are allowed on this VC.
TLP header will be rejected as an Unsupported Request.
Reserved
Port Arbitration Capability (PAC):
Having only bit 0 set indicates that the only supported
arbitration scheme for this VC is non-configurable hardware-
fixed.
0: Transactions with or without the No Snoop bit set within
1: Any transaction without the No Snoop bit set within the
0/0/0/DMIBAR
1C-1Fh
00008001h
RO
32 bits
Description
205

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