QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 356

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

10.2.9
10.3
10.3.1
10.3.1.1
356
System Memory Throttling
The Mobile Intel 945GM/GME/PM/GMS/GU/GSE, 943/940GML and Intel 945GT Express
Chipsets have two independent mechanisms, (i) (G)MCH Thermal Management and (ii)
DRAM Thermal Management that cause system memory bandwidth throttling. For more
information on System Memory Throttling, see
PCI Express-Based External Graphics
See the current PCI Express* Base Specification for details on PCI Express.
This (G)MCH is part of a PCI Express root complex. This means it connects a host CPU/
memory subsystem to a PCI Express Hierarchy. The control registers for this
functionality are located in Device 1 configuration space and two Root Complex
Register Blocks (RCRBs).
PCI Express Architecture
The PCI Express architecture is specified in layers. Compatibility with the PCI
addressing model (a load - store architecture with a flat address space) is maintained
to ensure that all existing applications and drivers operate unchanged. The PCI Express
configuration uses standard mechanisms as defined in the PCI Plug-and-Play
specification. The initial speed of 2.5 GHz (250 MHz internally) results in 2.5 GB/s
direction which provides a 250 MB/s communications channel in each direction
(500 MB/s total) that is close to twice the data rate of classic PCI per lane.
Layering Overview
The representation of layers in the PCI Express architecture (transaction layer, data link
layer, and physical layer) is to simplify the understanding of the high-level functionality.
PCI Express uses packets to communicate information between components. Packets
are formed in the transaction and data link layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side the reverse process occurs and
packets get transformed from their physical layer representation to the data link layer
representation and finally (for transaction layer packets) to the form that can be
processed by the transaction layer of the receiving device.
• (G)MCH Thermal management is to ensure that the chipset is operating within
• DRAM Thermal management is to ensure that the DRAM chips are operating within
thermal limits. The implementation provides a mechanism that controls the amount
of (G)MCH initiated DDR2 IO bandwidth to a programmable limit. The mechanism
can be initiated by a thermal sensor trip or by write bandwidth measurement
exceeding a programmed threshold.
thermal limits. DRAM s are organized as ranks. Each rank heats up independently
based on the activity it is subject to by the (G)MCH. A rank may heat up by
different amounts based on the type of activity it is subject to. For example the
amount of heat contributed by a read command is different when compared to a
write command to a rank. Throttling can be initiated by an external thermal sensor
trip or by DRAM activity measurement exceeding a programmed threshold.
Section
10.7.4.
Functional Description
Datasheet