QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 329

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

System Address Map
9.4
9.4.1
9.4.2
Datasheet
PCI Express Configuration Address Space
The Device 0 register (PCIEXBAR), defines the base address for the configuration space
associated with all devices and functions that are potentially a part of the PCI Express
root complex hierarchy. This is a 256-MB block of addresses below top of addressable
memory (currently 4 GB) and is aligned to a 256-MB boundary. BIOS must assign this
address range such that it will not conflict with any other address ranges.
For more configuration information, refer to
PCI Express Graphics Attach
The (G)MCH can be programmed to direct memory accesses to the PCI Express
interface when addresses are within either of two ranges specified via registers in
(G)MCH’s Device 1 configuration space.
The (G)MCH positively decodes memory accesses to PCI Express memory address
space as defined by the following equations:
Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
Prefetchable_Memory_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_Address
It is essential to support a separate Prefetchable range in order to apply USWC
attribute (from the processor point of view) to that range. The USWC attribute is used
by the processor for write combining.
Note that the (G)MCH Device 1 memory range registers described above are used to
allocate memory address space for any PCI Express devices sitting on PCI Express that
require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In
other words, the memory access enable bit must be set in the Device 1 PCICMD1
register to enable the memory base/limit and prefetchable base/limit windows.
AGP DRAM Graphics Aperture
Unlike AGP, PCI Express has no concept of aperture for PCI Express devices. As a
result, there is no need to translate addresses from PCI Express. Therefore, the
(G)MCH has no APBASE and APSIZE registers.
• The first range is controlled via the Memory Base register (MBASE) and Memory
• The second range is controlled via the Prefetchable Memory Base (PMBASE) and
Limit register (MLIMIT) registers.
Prefetchable Memory Limit (PMLIMIT) registers.
Chapter
4.
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