QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 69

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QG82945GSE S LB2R

Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
(G)MCH Configuration Process and Registers
4
4.1
Note:
.
Figure 4.
Datasheet
(G)MCH Configuration Process
and Registers
Platform Configuration Structure
The DMI physically connects the (G)MCH and the ICH; so, from a configuration
standpoint, the DMI is logically PCI Bus 0. As a result, all devices internal to the
(G)MCH and the ICH appear to be on PCI Bus 0. The system’s primary PCI expansion
bus is physically attached to the ICH and, from a configuration perspective, appears to
be a hierarchical PCI bus behind a PCI-to-PCI bridge and therefore has a programmable
PCI bus number. The PCI Express Graphics Attach appears to system software to be a
real PCI bus behind a PCI-to-PCI bridge that is a device resident on PCI Bus 0.
That a physical PCI Bus 0 does not exist and that DMI and the internal devices in the
(G)MCH and ICH logically constitute PCI Bus 0 to configuration software. This is shown
in the following figure.
Conceptual Mobile Intel 945GM/GME/PM/GMS/GU/GSE, 943/940GML and
Intel 945GT Express Chipset Platform PCI Configuration Diagram
Internal Graphics Configuration
(945GM/GMS/GT/GU/GSE/940
Host-PCI Express Bridge
LPC Device
Device 31
(945GM/PM/GT)
Bus0 Device2
Bus 0
Fcn 0
Registers
Device 1
Bus 0
GML)
PCI Configuration Window
Direct Media Interface
Direct Media Interface
in I/O Space
CPU
DRAM Controller
Interface Device
DMI — PCI
Bridge (P2)
Device 0
Device 30
Bus 0
fi
Bus 0
PBus 0
Fcn 0
GMCH
ICH
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