QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 12

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

10
12
9.10
Functional Description ........................................................................................... 337
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
9.9.1
(G)MCH Decode Rules and Cross-Bridge Address Mapping ..................................... 336
9.10.1 Legacy VGA and I/O Range Decode Rules ................................................ 336
Host Interface ................................................................................................. 337
10.1.1 FSB Source Synchronous Transfers ......................................................... 337
10.1.2 FSB IOQ Depth..................................................................................... 337
10.1.3 FSB OOQ Depth.................................................................................... 337
10.1.4 FSB GTL+ Termination .......................................................................... 337
10.1.5 FSB Dynamic Bus Inversion.................................................................... 337
10.1.6 FSB Interrupt Overview ......................................................................... 338
10.1.7 APIC Cluster Mode Support .................................................................... 338
System Memory Controller ................................................................................ 339
10.2.1 Functional Overview .............................................................................. 339
10.2.2 Functional Overview For Ultra Mobile Intel
10.2.3 Memory Channel Organization Modes ...................................................... 340
10.2.4 DRAM Technologies and Organization ...................................................... 342
10.2.5 DRAM Address Mapping ......................................................................... 344
10.2.6 DRAM Clock Generation ......................................................................... 353
10.2.7 DDR2 On Die Termination ...................................................................... 354
10.2.8 DRAM Power Management ..................................................................... 354
10.2.9 System Memory Throttling ..................................................................... 356
PCI Express-Based External Graphics ................................................................. 356
10.3.1 PCI Express Architecture........................................................................ 356
10.3.2 Serial Digital Video Output (SDVO).......................................................... 358
Integrated Graphics Controller........................................................................... 363
10.4.1 3D Graphics Processing ......................................................................... 364
Display Interfaces ............................................................................................ 372
10.5.1 Display Overview .................................................................................. 372
10.5.2 Planes ................................................................................................. 373
10.5.3 Display Pipes........................................................................................ 374
10.5.4 Display Ports........................................................................................ 375
10.5.5 Multiple Display Configurations ............................................................... 382
Power Management.......................................................................................... 382
10.6.1 Overview ............................................................................................. 382
10.6.2 ACPI States Supported .......................................................................... 382
10.6.3 Interface Power States Supported ........................................................... 383
10.6.4 Power Management Overview................................................................. 384
10.6.5 Chipset State Combinations ................................................................... 386
10.6.6 PWROK Timing Requirements for Power-up,
10.6.7 External Thermal Sensor PM_EXTTS1#:
10.6.8 Aux0 Trip on EXTTS0# .......................................................................... 389
10.6.9 CLKREQ# - Mode of Operation................................................................ 389
Thermal Management....................................................................................... 390
10.7.1 Internal Thermal Sensor ........................................................................ 390
10.7.2 External Thermal Sensor Interface Overview ............................................ 393
10.7.3 THRMTRIP# Operation........................................................................... 394
10.7.4 DT (Delta Temperature) in SPD and VTS (Virtual Thermal Sensor)............... 394
Clocking ......................................................................................................... 395
10.8.1 Overview ............................................................................................. 395
10.8.2 (G)MCH Reference Clocks ...................................................................... 395
10.8.3 Host/Memory/Graphics Core Clock Frequency Support ............................... 396
PCI Express I/O Address Mapping ........................................................... 335
Resume from S3-Cold and S3-Hot........................................................... 387
Implementation for Fast C4/C4E Exit ....................................................... 388
®
945GU Express Chipset ............ 340
Datasheet