QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 389
QG82945GSE S LB2R
Manufacturer Part Number
QG82945GSE S LB2R
Description
GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
Manufacturer
Intel
Datasheet
1.AU80586GE025DSLB73.pdf
(482 pages)
- Current page: 389 of 482
- Download datasheet (4Mb)
Functional Description
Figure 27.
10.6.8
Note:
10.6.9
Datasheet
EXTTS1# Implementation for Fast C4/C4E Exit
Aux0 Trip on EXTTS0#
With Fast C4/C4E Exit implemented, the EXTTS1# pin no longer functions as an
external thermal sensor event. This functionality is now available on the EXTTS#0 pin
via BIOS option. Please see register EXTTSCS; MCHBAR Offset CFFh and register ECO;
MCHBAR Offset FFCh.
EXTTS0# will not support Hot or Catastrophic trip points if Aux0 Trip on EXTTS0# is
enabled.
CLKREQ# - Mode of Operation
The CLKREQ# signal is driven by the (G)MCH to control the PCIe clock to the External
Graphics and the DMI clock. When both the DMI and PCIe links (if supported) are in L1,
with CPU in C3/C4/C4e state, the (G)MCH deasserts CLKREQ# to the clock chip, allow-
ing it to gate the GCLK differential clock pair to the (G)MCH, in turn disabling the PCIe
and DMI clocks inside the (G)MCH.
The following requirements must be met for the (G)MCH to support CLKREQ# function-
ality:
• ASPM is enabled on the platform
• Bit 19 of UPMC3 set to 1
PM_EXTTS1#
PM_EXTTS1#
GM CH
GM CH
500 O hm
500 O hm
DPRSLPVR
DPRSLPVR
DPRSLPVR
DPRSLPVR
IM VP6
IM VP6
ICH
ICH
389
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