QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 37

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

Signal Description
Datasheet
HDINV[3:0]#
HDRDY#
HA[31:3]#
HADSTB[1:0]#
HD[63:0]#
HDSTBP[3:0]#
HDSTBN[3:0]#
HHIT#
Signal Name
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
AGTL+
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
2X
2X
4X
4X
Host Dynamic Bus Inversion:
associated signals are inverted or not. HDINV[3:0]# are
asserted such that the number of data bits driven electrically low
(low voltage) within the corresponding 16-bit group never
exceeds 8.
HDINV#
HDINV[3]#
HDINV[2]#
HDINV[1]#
HDINV[0]#
Host Data Ready:
Asserted for each cycle that data is transferred.
Host Address Bus:
HA[31:3]# connects to the CPU address bus. During processor
cycles the HA[31:3]# are inputs. The (G)MCH drives HA[31:3]#
during snoop cycles on behalf of PCI Express*/Internal Graphics
or ICH7M. HA[31:3]# are transferred at 2x rate.
Note that the address is inverted on the CPU bus.
Host Address Strobe:
HA[31:3]# connects to the CPU address bus. During CPU cycles,
the source synchronous strobes are used to transfer HA[31:3]#
and HREQ[4:0]# at the 2x transfer rate.
Strobe
HADSTB[0]#
HADSTB[1]#
Host Data:
These signals are connected to the CPU data bus. HD[63:0]# are
transferred at 4x rate.
Note that the data signals are inverted on the CPU bus
depending on the HDINV[3:0]# signals.
Host Differential Host Data Strobes:
The differential source synchronous strobes are used to transfer
HD[63:0]# and HDINV[3:0]# at the 4x transfer rate.
Strobe
HDSTBP[3]#, HDSTBN[3]#
HDSTBP[2]#, HDSTBN[2]#
HDSTBP[1]#, HDSTBN[1]#
HDSTBP[0]#, HDSTBN[0]#
Host Hit:
Indicates that a caching agent holds an unmodified version of
the requested line.
Also, driven in conjunction with HITM# by the target to extend
the snoop window.
Driven along with the HD[63:0]# signals. Indicates if the
HD[63:48]#
HD[47:32]#
HD[31:16]#
Address Bits
Data Bits
HD[15:0]#
HA[15:3]#, HREQ[4:0]#
HA[31:16]#, HREQ[4:0]#
Description
HD[63:48]#, HDINV[3]#
HD[47:32]#, HDINV[2]#
HD[31:16]#, HDINV[1]#
HD[15:00]#, HDINV[0]#
Data Bits
37