QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 304

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

8.2.7
8.2.8
304
CLS - Cache Line Size
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The IGD does not support this register as a PCI slave.
MLT2 - Master Latency Timer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
7:0
7:0
Bit
Bit
Access
Access
RO
RO
Default
Default
Value
Value
00h
00h
Cache Line Size (CLS):
This field is hardwired to 0’s. The IGD as a PCI-compliant master
does not use the Memory Write and Invalidate command and, in
general, does not perform operations based on cache line size.
Master Latency Timer Count Value:
Hardwired to 0’s.
Internal Graphics Device 2 Configuration Register (D2:F0-F1)
0/2/1/PCI
Ch
00h
RO
8 bits
0/2/1/PCI
Dh
00h
RO
8 bits
Description
Description
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