QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 229

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

PCI Express Graphics Device 1 Configuration Registers (D1:F0)
Datasheet
Bit
8
7
6
5
4
3
2
Access
R/W
R/W
R/W
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
0b
0b
0b
SERR Message Enable (SERRE1):
Controls Device 1 SERR messaging. The (G)MCH communicates
the SERRB condition by sending an SERR message to the ICH.
This bit, when set, enables reporting of non-fatal and fatal errors
detected by the device to the Root Complex. Note that errors are
reported if enabled either through this bit or through the PCI-
Express specific bits in the Device Control register.
1 only under conditions enabled individually through the Device
Control register.
will be sent to the ICH for specific Device 1 error conditions
generated/detected on the primary side of the virtual PCI-to-PCI
bridge (not those received by the secondary side). The status of
SERRs generated is reported in the PCISTS1 register.
Reserved
Parity Error Enable (PERRE):
Controls whether or not the Master Data Parity Error bit in the
PCI Status register can bet set.
be set.
set.
VGA Palette Snoop (VGAPS):
Not Applicable or Implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE):
Not Applicable or Implemented. Hardwired to 0.
Special Cycle Enable (SCE):
Not Applicable or Implemented. Hardwired to 0.
Bus Master Enable (BME):
Controls the ability of the PEG port to forward Memory and IO
Read/Write Requests in the upstream direction.
requests to its primary bus.
According to the PCI Local Bus Specification, as MSI interrupt
messages are in-band memory writes, disabling the bus master
enable bit prevents this device from generating MSI interrupt
messages or passing them from its secondary bus to its primary
bus. Upstream memory writes/reads, IO writes/reads, peer
writes/reads, and MSIs will all be treated as illegal cycles. Writes
are forwarded to memory address 0 with byte enables
deasserted. Reads will be forwarded to memory address 0 and
will return Unsupported Request status (or Master abort) in its
completion packet.
Completions for previously issued memory read requests on the
primary bus will be issued when the data is available.
This bit does not affect forwarding of completions from the
primary interface to the secondary interface.
0: The SERR message is generated by the (G)MCH for Device
1: The (G)MCH is enabled to generate SERR messages which
0: Master Data Parity Error bit in PCI Status register cannot
1: Master Data Parity Error bit in PCI Status register can be
0: This device is prevented from making memory or IO
1: This device is allowed to issue requests to its primary bus.
(Sheet 2 of 3)
Description
229