QG82945GSE S LB2R Intel, QG82945GSE S LB2R Datasheet - Page 68

• Manufacturer Part Number: QG82945GSE S LB2R
• Description: GRAPHICS AND MEM CNTRL HUB; No. of Pins: 998; Package / Case: FCBGA; Interface Type: PCI, SATA, USB
• Manufacturer: Intel

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R/W/S
R/WSC
R/WSC/L
R/WC
R/WO
W
Abbreviation
Read / Write / Sticky bit(s). These bits can be read and written by
software. Bits are not cleared by “warm” reset, but will be reset with a cold/
complete reset (for PCI Express related bits a cold reset is “Power Good Reset”
as defined in the current PCI Local Bus Specification).
Read / Write Self Clear bit(s). These bits can be read and written by
software. When the bit is 1, hardware may clear the bit to 0 based upon
internal events, possibly sooner than any subsequent software read could
retrieve a 1.
Read / Write Self Clear / Lockable bit(s). These bits can be read and
written by software. When the bit is 1, hardware may clear the bit to 0 based
upon internal events, possibly sooner than any subsequent software read
could retrieve a 1. Additionally there is a bit (which is marked R/W/K or R/W/
L/K) that, when set, prohibits this bit field from being writable (bit field
becomes Read Only).
Read Write Clear bit(s). These bits can be read and written by software.
However, a write of 1 clears (sets to 0) the corresponding bit(s) and a write of
0 has no effect.
Write Once bit(s). Once written by software, bits with this attribute become
Read Only. These bits can only be cleared by a Reset.
Write Only. These bits may be written by software, but will always return 0’s
when read. They are used for write side-effects. Any data written to these
registers cannot be retrieved.
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(Sheet 2 of 2)
Definition
(G)MCH Register Description
Datasheet